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author | Kevin Lim <ktlim@umich.edu> | 2006-05-31 11:34:42 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-05-31 11:34:42 -0400 |
commit | d4b73086b6b0856c28433b55c8dd5c7b56a1b6df (patch) | |
tree | b54cb10579c6c5788fc09e7abd5d3a0ab1dd533c /src/python | |
parent | d77d39daee5c3ba8483d58911a1d5b12c4707040 (diff) | |
parent | 4a5b51b516853c9fcaabc44caacdd7e8e93dc0ef (diff) | |
download | gem5-d4b73086b6b0856c28433b55c8dd5c7b56a1b6df.tar.xz |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
--HG--
extra : convert_revision : 3d951bbeee0178de47e1bdbe704808544bfe732e
Diffstat (limited to 'src/python')
-rw-r--r-- | src/python/m5/objects/AlphaFullCPU.py | 39 |
1 files changed, 29 insertions, 10 deletions
diff --git a/src/python/m5/objects/AlphaFullCPU.py b/src/python/m5/objects/AlphaFullCPU.py index 48989d057..d719bf783 100644 --- a/src/python/m5/objects/AlphaFullCPU.py +++ b/src/python/m5/objects/AlphaFullCPU.py @@ -3,12 +3,16 @@ from BaseCPU import BaseCPU class DerivAlphaFullCPU(BaseCPU): type = 'DerivAlphaFullCPU' - + activity = Param.Unsigned("Initial count") numThreads = Param.Unsigned("number of HW thread contexts") if not build_env['FULL_SYSTEM']: mem = Param.FunctionalMemory(NULL, "memory") + checker = Param.BaseCPU(NULL, "checker") + + cachePorts = Param.Unsigned("Cache Ports") + decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") renameToFetchDelay = Param.Unsigned("Rename to fetch delay") iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " @@ -41,22 +45,25 @@ class DerivAlphaFullCPU(BaseCPU): executeFloatWidth = Param.Unsigned("Floating point execute width") executeBranchWidth = Param.Unsigned("Branch execute width") executeMemoryWidth = Param.Unsigned("Memory execute width") + fuPool = Param.FUPool(NULL, "Functional Unit pool") iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " "delay") renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") commitWidth = Param.Unsigned("Commit width") squashWidth = Param.Unsigned("Squash width") + trapLatency = Param.Tick("Trap latency") + fetchTrapLatency = Param.Tick("Fetch trap latency") - local_predictor_size = Param.Unsigned("Size of local predictor") - local_ctr_bits = Param.Unsigned("Bits per counter") - local_history_table_size = Param.Unsigned("Size of local history table") - local_history_bits = Param.Unsigned("Bits for the local history") - global_predictor_size = Param.Unsigned("Size of global predictor") - global_ctr_bits = Param.Unsigned("Bits per counter") - global_history_bits = Param.Unsigned("Bits of history") - choice_predictor_size = Param.Unsigned("Size of choice predictor") - choice_ctr_bits = Param.Unsigned("Bits of choice counters") + localPredictorSize = Param.Unsigned("Size of local predictor") + localCtrBits = Param.Unsigned("Bits per counter") + localHistoryTableSize = Param.Unsigned("Size of local history table") + localHistoryBits = Param.Unsigned("Bits for the local history") + globalPredictorSize = Param.Unsigned("Size of global predictor") + globalCtrBits = Param.Unsigned("Bits per counter") + globalHistoryBits = Param.Unsigned("Bits of history") + choicePredictorSize = Param.Unsigned("Size of choice predictor") + choiceCtrBits = Param.Unsigned("Bits of choice counters") BTBEntries = Param.Unsigned("Number of BTB entries") BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") @@ -68,6 +75,8 @@ class DerivAlphaFullCPU(BaseCPU): LFSTSize = Param.Unsigned("Last fetched store table size") SSITSize = Param.Unsigned("Store set ID table size") + numRobs = Param.Unsigned("Number of Reorder Buffers"); + numPhysIntRegs = Param.Unsigned("Number of physical integer registers") numPhysFloatRegs = Param.Unsigned("Number of physical floating point " "registers") @@ -78,3 +87,13 @@ class DerivAlphaFullCPU(BaseCPU): function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Cycle to start function trace") + + smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads") + smtFetchPolicy = Param.String("SMT Fetch policy") + smtLSQPolicy = Param.String("SMT LSQ Sharing Policy") + smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter") + smtIQPolicy = Param.String("SMT IQ Sharing Policy") + smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter") + smtROBPolicy = Param.String("SMT ROB Sharing Policy") + smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") + smtCommitPolicy = Param.String("SMT Commit Policy") |