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authorRon Dreslinski <rdreslin@umich.edu>2006-11-14 01:13:26 -0500
committerRon Dreslinski <rdreslin@umich.edu>2006-11-14 01:13:26 -0500
commitac309071afe9d28e4635337c1c645a8cfc526a0f (patch)
treea1907b2e8a99edbf1e3b8870e35ca7b42efa5743 /src/python
parent4135dd48ed0e876e11a935240d5436a421db12c6 (diff)
downloadgem5-ac309071afe9d28e4635337c1c645a8cfc526a0f.tar.xz
Update phase param in the .py file for the cpus
--HG-- extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803
Diffstat (limited to 'src/python')
-rw-r--r--src/python/m5/objects/BaseCPU.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 2f702a4bf..8037c90af 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -47,6 +47,7 @@ class BaseCPU(SimObject):
"defer registration with system (for sampling)")
clock = Param.Clock(Parent.clock, "clock speed")
+ phase = Param.Latency("0ns", "clock phase")
_mem_ports = []