summaryrefslogtreecommitdiff
path: root/src/python
diff options
context:
space:
mode:
authorSteve Reinhardt <stever@eecs.umich.edu>2006-08-16 14:16:52 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2006-08-16 14:16:52 -0700
commitdf3af8018e5a252f7c4e8f52b872263c8ab375cc (patch)
treebdc61fb372fc0f8e603cbcdf97e5d3883accf5a5 /src/python
parent597ef651df487937399e371fd11711cb8908b581 (diff)
downloadgem5-df3af8018e5a252f7c4e8f52b872263c8ab375cc.tar.xz
Minor regression fixes.
src/python/m5/objects/BaseCPU.py: bug fix tests/SConscript: fix up diff ignore strings to reflect changes in m5 output --HG-- extra : convert_revision : b8e4acee34599ddd431b69fc9d40b6f6e440d128
Diffstat (limited to 'src/python')
-rw-r--r--src/python/m5/objects/BaseCPU.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 7906156a2..01458aeb4 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -49,5 +49,5 @@ class BaseCPU(SimObject):
self.toL2Bus = Bus()
self.connectMemPorts(self.toL2Bus)
self.l2cache = l2c
- self.l2cache.cpu_side = toL2Bus.port
+ self.l2cache.cpu_side = self.toL2Bus.port
self._mem_ports = ['l2cache.mem_side']