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| author | Tuan Ta <qtt2@cornell.edu> | 2018-04-02 15:18:57 -0400 |
|---|---|---|
| committer | Tuan Ta <qtt2@cornell.edu> | 2018-06-14 22:42:16 +0000 |
| commit | 642a563cf08171f1a89ae67229e93187cae28bd8 (patch) | |
| tree | 980800270fd015745c9ba8914a88e4ef2d96ad70 /src/sim/ClockDomain.py | |
| parent | 7341f14f147337810325b19bac20db095b162911 (diff) | |
| download | gem5-642a563cf08171f1a89ae67229e93187cae28bd8.tar.xz | |
cpu: Prevent suspended TimingSimple CPUs from fetching next instructions
In TimingSimpleCPU model, when a CPU is suspended by a syscall (e.g.,
futex(FUTEX_WAIT)), the CPU waits for another CPU to wake it up
(e.g., FUTEX_WAKE operation). While staying Idle, the suspended CPU
should not try to fetch next instructions after the syscall.
This patch added a status check before a CPU schedule a fetch event
after a fault is handled.
Change-Id: I0cc953135686c9b35afe94942aa1d0b245ec60a2
Reviewed-on: https://gem5-review.googlesource.com/8181
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Diffstat (limited to 'src/sim/ClockDomain.py')
0 files changed, 0 insertions, 0 deletions