power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
                             tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True

1 files changed, 20 insertions, 3 deletions

diff --git a/src/sim/ClockDomain.py b/src/sim/ClockDomain.py
index 2a3b6addf..4d2b24914 100644
--- a/src/sim/ClockDomain.py
+++ b/src/sim/ClockDomain.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2013 ARM Limited
+# Copyright (c) 2013-2014 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -35,6 +35,7 @@
 #
 # Authors: Vasileios Spiliopoulos
 #          Akash Bagdia
+#          Stephan Diestelhorst
 
 from m5.params import *
 from m5.SimObject import SimObject
@@ -46,15 +47,31 @@ class ClockDomain(SimObject):
     cxx_header = "sim/clock_domain.hh"
     abstract = True
 
-# Source clock domain with an actual clock
+# Source clock domain with an actual clock, and a list of voltage and frequency
+# op points
 class SrcClockDomain(ClockDomain):
     type = 'SrcClockDomain'
     cxx_header = "sim/clock_domain.hh"
-    clock = Param.Clock("Clock period")
+
+    # Single clock frequency value, or list of frequencies for DVFS
+    # Frequencies must be ordered in descending order
+    # Note: Matching voltages should be defined in the voltage domain
+    clock = VectorParam.Clock("Clock period")
 
     # A source clock must be associated with a voltage domain
     voltage_domain = Param.VoltageDomain("Voltage domain")
 
+    # Domain ID is an identifier for the DVFS domain as understood by the
+    # necessary control logic (either software or hardware). For example, in
+    # case of software control via cpufreq framework the IDs should correspond
+    # to the neccessary identifier in the device tree blob which is interpretted
+    # by the device driver to communicate to the domain controller in hardware.
+    domain_id = Param.Int32(-1, "domain id")
+
+    # Initial performance level from the list of available operation points
+    # Defaults to maximum performance
+    init_perf_level = Param.UInt32(0, "Initial performance level")
+
 # Derived clock domain with a parent clock domain and a frequency
 # divider
 class DerivedClockDomain(ClockDomain):