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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:07:07 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:07:07 -0400 |
commit | 930db9257dbac7e678888a65a17c39bcc87aa7fa (patch) | |
tree | 0963906363267079f8cab73332e926320cbd242e /src/sim/ClockedObject.py | |
parent | 8cc503f1dd535690a9e50188d0216844057125f8 (diff) | |
download | gem5-930db9257dbac7e678888a65a17c39bcc87aa7fa.tar.xz |
Clock: Inherit the clock from parent by default
This patch changes the default 1 Tick clock period to a proxy that
resolves the parents clock. As a result of this, the caches and
L1-to-L2 bus, for example, will automatically use the clock period of
the CPU unless explicitly overridden.
To ensure backwards compatibility, the System class overrides the
proxy and specifies a 1 Tick clock. We could change this to something
more reasonable in a follow-on patch, perhaps 1 GHz or something
similar.
With this patch applied, all clocked objects should have a reasonable
clock period set, and could start specifying delays in Cycles instead
of absolute time.
Diffstat (limited to 'src/sim/ClockedObject.py')
-rw-r--r-- | src/sim/ClockedObject.py | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py index 9bb243df8..26b0e2348 100644 --- a/src/sim/ClockedObject.py +++ b/src/sim/ClockedObject.py @@ -37,9 +37,13 @@ from m5.SimObject import SimObject from m5.params import * +from m5.proxy import * class ClockedObject(SimObject): type = 'ClockedObject' abstract = True - clock = Param.Clock('1t', "Clock speed") + # Clock period of this object, with the default value being the + # clock period of the parent object, unproxied at instantiation + # time + clock = Param.Clock(Parent.clock, "Clock speed") |