power: Add power states to ClockedObject

Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.

Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.

Add dump call back function to allow stats update of distribution and residency
stats.

1 files changed, 28 insertions, 1 deletions

diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py
index 2562f1f01..b933ea07a 100644
--- a/src/sim/ClockedObject.py
+++ b/src/sim/ClockedObject.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2015 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -39,6 +39,24 @@ from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
 
+# Enumerate set of allowed power states that can be used by a clocked object.
+# The list is kept generic to express a base minimal set.
+# State definition :-
+#   Undefined: Invalid state, no power state derived information is available.
+#   On: The logic block is actively running and consuming dynamic and leakage
+#       energy depending on the amount of processing required.
+#   Clk_gated: The clock circuity within the block is gated to save dynamic
+#              energy, the power supply to the block is still on and leakage
+#              energy is being consumed by the block.
+#   Sram_retention: The SRAMs within the logic blocks are pulled into retention
+#                   state to reduce leakage energy further.
+#   Off: The logic block is power gated and is not consuming any energy.
+class PwrState(Enum): vals = ['UNDEFINED',
+                             'ON',
+                             'CLK_GATED',
+                             'SRAM_RETENTION',
+                             'OFF']
+
 class ClockedObject(SimObject):
     type = 'ClockedObject'
     abstract = True
@@ -47,3 +65,12 @@ class ClockedObject(SimObject):
     # The clock domain this clocked object belongs to, inheriting the
     # parent's clock domain by default
     clk_domain = Param.ClockDomain(Parent.clk_domain, "Clock domain")
+
+    # Provide initial power state, should ideally get redefined in startup
+    # routine
+    default_p_state = Param.PwrState("UNDEFINED", "Default Power State")
+
+    p_state_clk_gate_min = Param.Latency('1ns', "Min value of the distribution")
+    p_state_clk_gate_max = Param.Latency('1s', "Max value of the distribution")
+    p_state_clk_gate_bins = Param.Unsigned('20',
+        "# bins in clk gated distribution")