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authorAndreas Hansson <andreas.hansson@arm.com>2013-02-19 05:56:06 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2013-02-19 05:56:06 -0500
commit40d0e6c899d5da400c9647496532a8fb1ef64b7b (patch)
tree2d449d0c6ef57cb5261541e1bd1899878766bb8b /src/sim/Process.py
parentb3fc8839c4727da575ed916cbd6a76d8ad5fc644 (diff)
downloadgem5-40d0e6c899d5da400c9647496532a8fb1ef64b7b.tar.xz
mem: Change accessor function names to match the port interface
This patch changes the names of the cache accessor functions to be in line with those used by the ports. This is done to avoid confusion and get closer to a one-to-one correspondence between the interface of the memory object (the cache in this case) and the port itself. The member function timingAccess has been split into a snoop/non-snoop part to avoid branching on the isResponse() of the packet.
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