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| author | Alexandru <alexandru.dutu@amd.com> | 2014-08-28 10:11:44 -0500 |
|---|---|---|
| committer | Alexandru <alexandru.dutu@amd.com> | 2014-08-28 10:11:44 -0500 |
| commit | 5efbb4442a0e8c653539e263bf87c48849280e23 (patch) | |
| tree | da6807c806ebb1f658692c5bf823156831134c9f /src/sim/Process.py | |
| parent | 26ac28dec288e4fd96d999267ec7cafad4d58c5a (diff) | |
| download | gem5-5efbb4442a0e8c653539e263bf87c48849280e23.tar.xz | |
mem: adding architectural page table support for SE mode
This patch enables the use of page tables that are stored in system memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.
Diffstat (limited to 'src/sim/Process.py')
| -rw-r--r-- | src/sim/Process.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/sim/Process.py b/src/sim/Process.py index 55ccc50d0..6f2322805 100644 --- a/src/sim/Process.py +++ b/src/sim/Process.py @@ -38,6 +38,8 @@ class Process(SimObject): output = Param.String('cout', 'filename for stdout') errout = Param.String('cerr', 'filename for stderr') system = Param.System(Parent.any, "system process will run on") + useArchPT = Param.Bool('false', 'maintain an in-memory version of the page\ + table in an architecture-specific format') max_stack_size = Param.MemorySize('64MB', 'maximum size of the stack') @classmethod |