diff options
| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-02-11 10:23:27 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-02-11 10:23:27 -0500 |
| commit | 550c31849024a2184887df87aae39617ebfe0d6a (patch) | |
| tree | 53cc5e91d0961b0215c614141fdc380b30c76951 /src/sim/SConscript | |
| parent | 9e6f803254cbf3f5f491775debdc6593c3329da8 (diff) | |
| download | gem5-550c31849024a2184887df87aae39617ebfe0d6a.tar.xz | |
sim: Move the BaseTLB to src/arch/generic/
The TLB-related code is generally architecture dependent and should
live in the arch directory to signify that.
--HG--
rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py
rename : src/sim/tlb.cc => src/arch/generic/tlb.cc
rename : src/sim/tlb.hh => src/arch/generic/tlb.hh
Diffstat (limited to 'src/sim/SConscript')
| -rw-r--r-- | src/sim/SConscript | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/sim/SConscript b/src/sim/SConscript index 7583b53cb..400d595e3 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -30,7 +30,6 @@ Import('*') -SimObject('BaseTLB.py') SimObject('ClockedObject.py') SimObject('TickedObject.py') SimObject('Root.py') @@ -75,7 +74,6 @@ if env['TARGET_ISA'] != 'null': Source('process.cc') Source('pseudo_inst.cc') Source('syscall_emul.cc') - Source('tlb.cc') DebugFlag('Checkpoint') DebugFlag('Config') @@ -92,7 +90,6 @@ DebugFlag('PseudoInst') DebugFlag('Stack') DebugFlag('SyscallVerbose') DebugFlag('TimeSync') -DebugFlag('TLB') DebugFlag('Thread') DebugFlag('Timer') DebugFlag('VtoPhys') |