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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2008-12-17 09:51:18 -0800 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2008-12-17 09:51:18 -0800 |
| commit | 1704ba2273d9623095ddcd269055aedb8e818e03 (patch) | |
| tree | b5ce140d4945bb793b60477b6f69fd7c1730c0d3 /src/sim/SConscript | |
| parent | 02cd18f536544d4b5fa19681b4c9dbd5b2cb87ff (diff) | |
| download | gem5-1704ba2273d9623095ddcd269055aedb8e818e03.tar.xz | |
Make Alpha pseudo-insts available from SE mode.
Diffstat (limited to 'src/sim/SConscript')
| -rw-r--r-- | src/sim/SConscript | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/sim/SConscript b/src/sim/SConscript index 7acf4e9b6..48200161c 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -43,6 +43,7 @@ Source('eventq.cc') Source('faults.cc') Source('init.cc') BinSource('main.cc') +Source('pseudo_inst.cc') Source('root.cc') Source('serialize.cc') Source('sim_events.cc') @@ -54,7 +55,6 @@ Source('system.cc') if env['FULL_SYSTEM']: Source('arguments.cc') - Source('pseudo_inst.cc') else: Source('tlb.cc') SimObject('Process.py') |