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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
| commit | d080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch) | |
| tree | cc484b289fa5a30c4631f9faa1d8b456bffeebfc /src/sim/SConscript | |
| parent | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff) | |
| parent | 639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff) | |
| download | gem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz | |
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'src/sim/SConscript')
| -rw-r--r-- | src/sim/SConscript | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/sim/SConscript b/src/sim/SConscript index 0b39ab8e8..750007947 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -30,6 +30,7 @@ Import('*') +SimObject('BaseTLB.py') SimObject('Root.py') SimObject('System.py') SimObject('InstTracer.py') @@ -39,7 +40,9 @@ Source('core.cc') Source('debug.cc') Source('eventq.cc') Source('faults.cc') -Source('main.cc') +Source('init.cc') +BinSource('main.cc') +Source('pseudo_inst.cc') Source('root.cc') Source('serialize.cc') Source('sim_events.cc') @@ -51,7 +54,6 @@ Source('system.cc') if env['FULL_SYSTEM']: Source('arguments.cc') - Source('pseudo_inst.cc') else: Source('tlb.cc') SimObject('Process.py') |