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| author | Ruslan Bukin <br@bsdpad.com> | 2015-04-03 11:42:10 -0500 |
|---|---|---|
| committer | Ruslan Bukin <br@bsdpad.com> | 2015-04-03 11:42:10 -0500 |
| commit | b3314673f456a9686559ec95cbee2302c3214921 (patch) | |
| tree | 20fca4d16a2dce3037a8e7f7e274779424af1d00 /src/sim/System.py | |
| parent | 305e29b98ef369bcf5574a0a462f43c0bbc7ba5b (diff) | |
| download | gem5-b3314673f456a9686559ec95cbee2302c3214921.tar.xz | |
dev: Extend access width for IDE control registers
Add 32-bit access width for PrimaryTiming register and 16bit for UDMAControl
register as FreeBSD required.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/sim/System.py')
0 files changed, 0 insertions, 0 deletions