summaryrefslogtreecommitdiff
path: root/src/sim/System.py
diff options
context:
space:
mode:
authorSteve Reinhardt <stever@eecs.umich.edu>2007-06-21 12:03:22 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2007-06-21 12:03:22 -0700
commiteff122797b5bc735c6d7c797be691c0fa02032e3 (patch)
tree1dd1cef3b2b4e044fece9a406cd0ce97d09a2da7 /src/sim/System.py
parent83af0fdcf57175adf8077c51e9ba872dd2c04b76 (diff)
parent5195500cdf7dc99b5367f91387eef4e9f5b65bfe (diff)
downloadgem5-eff122797b5bc735c6d7c797be691c0fa02032e3.tar.xz
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920
Diffstat (limited to 'src/sim/System.py')
-rw-r--r--src/sim/System.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/sim/System.py b/src/sim/System.py
index b37e385c1..3f4c57f0c 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -39,6 +39,7 @@ class System(SimObject):
physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
if build_env['FULL_SYSTEM']:
+ abstract = True
boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
"boot processor frequency")
init_param = Param.UInt64(0, "numerical value to pass into simulator")