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authorAndreas Hansson <andreas.hansson@arm.com>2012-01-17 12:55:07 -0600
committerAndreas Hansson <andreas.hansson@arm.com>2012-01-17 12:55:07 -0600
commit13ef7a56478fdd993a726833e14a85307446c28f (patch)
treef347d4ecd903ba1d76fe90e2d7c5c9217af8c77d /src/sim/System.py
parent8c7936c40c7e63d7b8e11cc3d234fbe8de7d0f45 (diff)
downloadgem5-13ef7a56478fdd993a726833e14a85307446c28f.tar.xz
MEM: Differentiate functional cache accesses from CPU and memory
This patch changes the functionalAccess member function in the cache model such that it is aware of what port the access came from, i.e. if it came from the CPU side or from the memory side. By adding this information, it is possible to respect the 'forwardSnoops' flag for snooping requests coming from the memory side and not forward them. This fixes an outstanding issue with the IO bus getting accesses that have no valid destination port and also cleans up future changes to the bus model.
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