Clock: Inherit the clock from parent by default

This patch changes the default 1 Tick clock period to a proxy that
resolves the parents clock. As a result of this, the caches and
L1-to-L2 bus, for example, will automatically use the clock period of
the CPU unless explicitly overridden.

To ensure backwards compatibility, the System class overrides the
proxy and specifies a 1 Tick clock. We could change this to something
more reasonable in a follow-on patch, perhaps 1 GHz or something
similar.

With this patch applied, all clocked objects should have a reasonable
clock period set, and could start specifying delays in Cycles instead
of absolute time.

1 files changed, 7 insertions, 0 deletions

diff --git a/src/sim/System.py b/src/sim/System.py
index f680e64bf..88afea873 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -41,6 +41,13 @@ class System(MemObject):
     type = 'System'
     system_port = MasterPort("System port")
 
+    # Override the clock from the ClockedObject which looks at the
+    # parent clock by default
+    clock = '1t'
+    # @todo Either make this value 0 and treat it as an error if it is
+    # not overridden, or choose a more sensible value in the range of
+    # 1GHz
+
     @classmethod
     def export_method_cxx_predecls(cls, code):
         code('#include "sim/system.hh"')