summaryrefslogtreecommitdiff
path: root/src/sim/System.py
diff options
context:
space:
mode:
authorAkash Bagdia <akash.bagdia@arm.com>2013-06-27 05:49:49 -0400
committerAkash Bagdia <akash.bagdia@arm.com>2013-06-27 05:49:49 -0400
commit076d04a653f5a4252c6c16e010ad0d7bf36c1674 (patch)
tree1be09e01ab286960ae6fcd5d767bfb0e10270ec2 /src/sim/System.py
parent4459b305251109ff147d72142452e25c74542ebd (diff)
downloadgem5-076d04a653f5a4252c6c16e010ad0d7bf36c1674.tar.xz
config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign clocks to the system during instantiation. As part of this change, the default clock in the System class is removed and whenever a system is instantiated a system clock value must be set. A default value is provided for the command-line option. The configs and tests are updated accordingly.
Diffstat (limited to 'src/sim/System.py')
-rw-r--r--src/sim/System.py6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/sim/System.py b/src/sim/System.py
index 031331375..2cc171881 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -43,12 +43,6 @@ class System(MemObject):
cxx_header = "sim/system.hh"
system_port = MasterPort("System port")
- # Override the clock from the ClockedObject which looks at the
- # parent clock by default. The 1 GHz default system clock serves
- # as a start for the modules that rely on the parent to provide
- # the clock.
- clock = '1GHz'
-
@classmethod
def export_method_cxx_predecls(cls, code):
code('#include "sim/system.hh"')