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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:07 -0600 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:07 -0600 |
| commit | 41af57f9fbc8220fbac8a3061ddadf4a4d942ebf (patch) | |
| tree | c35bc2f0c1480e6abc183f47b2eaa0286fb2b132 /src/sim/System.py | |
| parent | 13ef7a56478fdd993a726833e14a85307446c28f (diff) | |
| download | gem5-41af57f9fbc8220fbac8a3061ddadf4a4d942ebf.tar.xz | |
MEM: Add the system port as a central access point
The system port is used as a globally reachable access point to the
memory subsystem. The benefit of using an actual port is that the
usual infrastructure is used to resolve any access and thus makes the
overall system able to handle distributed memories in any
configuration, and also makes the accesses agnostic to the address
map. This patch only introduces the port and does not actually use it
for anything.
Diffstat (limited to 'src/sim/System.py')
| -rw-r--r-- | src/sim/System.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/sim/System.py b/src/sim/System.py index 3caa907d7..d34a043c1 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -37,8 +37,9 @@ from PhysicalMemory import * class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] -class System(SimObject): +class System(MemObject): type = 'System' + system_port = Port("System port") @classmethod def export_method_cxx_predecls(cls, code): |