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authorAli Saidi <Ali.Saidi@ARM.com>2011-07-10 12:56:08 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-07-10 12:56:08 -0500
commit60579e8d74cecea5737a4502599ccf77e9e6a35e (patch)
tree34e86b09774b7a10ba1948b189d00006d19ed684 /src/sim/System.py
parent9751a1d3e78cbbcd17835ab967f036945ee2cec2 (diff)
downloadgem5-60579e8d74cecea5737a4502599ccf77e9e6a35e.tar.xz
O3: Make sure fetch doesn't go off into the weeds during speculation.
Diffstat (limited to 'src/sim/System.py')
-rw-r--r--src/sim/System.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/sim/System.py b/src/sim/System.py
index fd707c353..a6897d834 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -44,8 +44,9 @@ class System(SimObject):
def swig_objdecls(cls, code):
code('%include "python/swig/system.i"')
- physmem = Param.PhysicalMemory(Parent.any, "physical memory")
+ physmem = Param.PhysicalMemory("Physical Memory")
mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
+ memories = VectorParam.PhysicalMemory(Self.all, "All memories is the system")
work_item_id = Param.Int(-1, "specific work item id")
work_begin_cpu_id_exit = Param.Int(-1,