power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
                             tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True

1 files changed, 5 insertions, 0 deletions

diff --git a/src/sim/System.py b/src/sim/System.py
index 95162be89..b8f15c209 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -33,6 +33,7 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 
+from DVFSHandler import *
 from SimpleMemory import *
 
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
@@ -88,3 +89,7 @@ class System(MemObject):
     load_addr_mask = Param.UInt64(0xffffffffff,
             "Address to mask loading binaries with")
     load_offset = Param.UInt64(0, "Address to offset loading binaries with")
+
+    # Dynamic voltage and frequency handler for the system, disabled by default
+    # Provide list of domains that need to be controlled by the handler
+    dvfs_handler = DVFSHandler()