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authorAndreas Hansson <andreas.hansson@arm.com>2015-07-03 10:14:40 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-07-03 10:14:40 -0400
commit0ddde83a47e8a129de1a5c00475772c6ac0fd004 (patch)
tree0b49eb8b61a7a8ce9ec2e0b340999b9b78d8c7ab /src/sim/emul_driver.hh
parent893533a1264bb369b47f74493adf30ce22829f34 (diff)
downloadgem5-0ddde83a47e8a129de1a5c00475772c6ac0fd004.tar.xz
mem: Add ReadCleanReq and ReadSharedReq packets
This patch adds two new read requests packets: ReadCleanReq - For a cache to explicitly request clean data. The response is thus exclusive or shared, but not owned or modified. The read-only caches (see previous patch) use this request type to ensure they do not get dirty data. ReadSharedReq - We add this to distinguish cache read requests from those issued by other masters, such as devices and CPUs. Thus, devices use ReadReq, and caches use ReadCleanReq, ReadExReq, or ReadSharedReq. For the latter, the response can be any state, shared, exclusive, owned or even modified. Both ReadCleanReq and ReadSharedReq re-use the normal ReadResp. The two transactions are aligned with the emerging cache-coherent TLM standard and the AMBA nomenclature. With this change, the normal ReadReq should never be used by a cache, and is reserved for the actual (non-caching) masters in the system. We thus have a way of identifying if a request came from a cache or not. The introduction of ReadSharedReq thus removes the need for the current isTopLevel hack, and also allows us to stop relying on checking the packet size to determine if the source is a cache or not. This is fixed in follow-on patches.
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