summaryrefslogtreecommitdiff
path: root/src/sim/eventq.cc
diff options
context:
space:
mode:
authorGabe Black <gabeblack@google.com>2018-10-18 17:50:42 -0700
committerGabe Black <gabeblack@google.com>2019-01-22 21:16:10 +0000
commit1ab1500dfd0cb64b2fef7fb5e0f9e1fa007d2481 (patch)
treee2c9cbab3738a79463e6ad9defbe845efb764a51 /src/sim/eventq.cc
parent230b892fa3f484a46f4cd77f889f8793416b91e2 (diff)
downloadgem5-1ab1500dfd0cb64b2fef7fb5e0f9e1fa007d2481.tar.xz
sparc: Get rid of some register type definitions.
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/sim/eventq.cc')
0 files changed, 0 insertions, 0 deletions