power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
                             tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True

1 files changed, 4 insertions, 0 deletions

diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 9b3cd9917..eaefdb2e2 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -144,6 +144,10 @@ class EventBase
     /// Default is zero for historical reasons.
     static const Priority Default_Pri =                  0;
 
+    /// DVFS update event leads to stats dump therefore given a lower priority
+    /// to ensure all relevant states have been updated
+    static const Priority DVFS_Update_Pri =             31;
+
     /// Serailization needs to occur before tick events also, so
     /// that a serialize/unserialize is identical to an on-line
     /// CPU switch.