LSQ: Only trigger a memory violation with a load/load if the value changes.

Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).

1 files changed, 10 insertions, 0 deletions

diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index 7f431b313..f5e9aded1 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -75,6 +75,16 @@ class UnimpFault : public FaultBase
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
+class ReExec : public FaultBase
+{
+  public:
+    virtual FaultName name() const { return "Re-execution fault";}
+    ReExec() {}
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
+};
+
+
 #if !FULL_SYSTEM
 class GenericPageTableFault : public FaultBase
 {