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author | Matteo Andreozzi <Matteo.Andreozzi@arm.com> | 2018-01-10 13:38:47 +0000 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-07 13:16:20 +0000 |
commit | 66f80b5a731e2fac5d9e4f841804d87a1267b76a (patch) | |
tree | 6350563636c536a726149a38c5a3d96d8f99348a /src/sim/init_signals.hh | |
parent | 53cdcdee663c614d134174edea57b98a15385679 (diff) | |
download | gem5-66f80b5a731e2fac5d9e4f841804d87a1267b76a.tar.xz |
mem: Add a QoS-aware Memory Controller type
This is the implementation of QoS algorithms support for gem5 memory
objects. This change-list provides a framework for specifying QoS
algorithm which can be used to prioritise service to specific masters in
the memory controller.
The QoS support implemented here is designed to be extendable so that
new QoS algorithms can be easily plugged into the memory controller as
"QoS Policies".
Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11970
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/sim/init_signals.hh')
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