CPU: Create a microcode ROM object in the CPU which is defined by the ISA.

1 files changed, 52 insertions, 0 deletions

diff --git a/src/sim/microcode_rom.hh b/src/sim/microcode_rom.hh
new file mode 100644
index 000000000..be10de86b
--- /dev/null
+++ b/src/sim/microcode_rom.hh
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __SIM_MICROCODE_ROM_HH__
+#define __SIM_MICROCODE_ROM_HH__
+
+/*
+ * This is a generic stub microcode ROM ISAs can use if they don't need
+ * anything more.
+ */
+
+#include "base/misc.hh"
+#include "cpu/static_inst.hh"
+
+class MicrocodeRom
+{
+  public:
+    StaticInstPtr
+    fetchMicroop(MicroPC micropc, StaticInstPtr curMacroop)
+    {
+        panic("ROM based microcode isn't implemented.\n");
+    }
+};
+
+#endif // __SIM_MICROCODE_ROM_HH__