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author | Steve Reinhardt <steve.reinhardt@amd.com> | 2011-10-20 13:08:49 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2011-10-20 13:08:49 -0700 |
commit | 45d14e02c4eef63c9d0db4e9155bf5fe93673c10 (patch) | |
tree | 606567661a75548626e47b1b7b525f542985ed69 /src/sim/microcode_rom.hh | |
parent | f2bfef90c4441ea77025ebb3de398f9d66bbffdf (diff) | |
download | gem5-45d14e02c4eef63c9d0db4e9155bf5fe93673c10.tar.xz |
scons/swig: refactor some of the scons/SWIG code
- Move the random bits of SWIG code generation out of src/SConscript
file and into methods on the objects being wrapped.
- Cleaned up some variable naming and added some comments to make
the process a little clearer.
- Did a little generated file/module renaming:
- vptype_Foo now Foo_vector
- init_Foo is now Foo_init
This makes it easier to see all the Foo-related files in a
sorted directory listing.
- Made cxx_predecls and swig_predecls normal SimObject classmethods.
- Got rid of swig_objdecls hook, even though this breaks the System
objects get/setMemoryMode method exports. Will be fixing this in
a future changeset.
Diffstat (limited to 'src/sim/microcode_rom.hh')
0 files changed, 0 insertions, 0 deletions