diff options
| author | Alexandru <alexandru.dutu@amd.com> | 2014-04-01 12:18:12 -0500 |
|---|---|---|
| committer | Alexandru <alexandru.dutu@amd.com> | 2014-04-01 12:18:12 -0500 |
| commit | 26ac28dec288e4fd96d999267ec7cafad4d58c5a (patch) | |
| tree | 937c3fc79a1d4622215c0e23ac6ae6e5945aab68 /src/sim/process.cc | |
| parent | 6dc90da08f5e743111ab9ae2623d5c0dad808d29 (diff) | |
| download | gem5-26ac28dec288e4fd96d999267ec7cafad4d58c5a.tar.xz | |
mem: adding a multi-level page table class
This patch defines a multi-level page table class that stores the page table in
system memory, consistent with ISA specifications. In this way, cpu models that
use the actual hardware to execute (e.g. KvmCPU), are able to traverse the page
table.
Diffstat (limited to 'src/sim/process.cc')
| -rw-r--r-- | src/sim/process.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/sim/process.cc b/src/sim/process.cc index ccaac2096..d9f9a0fe6 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -1,4 +1,5 @@ /* + * Copyright (c) 2014 Advanced Micro Devices, Inc. * Copyright (c) 2012 ARM Limited * All rights reserved * @@ -55,6 +56,7 @@ #include "config/the_isa.hh" #include "cpu/thread_context.hh" #include "mem/page_table.hh" +#include "mem/multi_level_page_table.hh" #include "mem/se_translating_port_proxy.hh" #include "params/LiveProcess.hh" #include "params/Process.hh" @@ -104,7 +106,7 @@ Process::Process(ProcessParams * params) : SimObject(params), system(params->system), max_stack_size(params->max_stack_size), M5_pid(system->allocatePID()), - pTable(new PageTable(name(), M5_pid)), + pTable(new FuncPageTable(name(), M5_pid)), initVirtMem(system->getSystemPort(), this, SETranslatingPortProxy::Always) { @@ -246,6 +248,8 @@ Process::initState() // mark this context as active so it will start ticking. tc->activate(Cycles(0)); + + pTable->initState(tc); } // map simulator fd sim_fd to target fd tgt_fd |