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author | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
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committer | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
commit | 1f539f13c32ad5a9187d56a098d4c857639b0e05 (patch) | |
tree | 7618c3b946d9c25d9b22018f226eee77b6de4aaf /src/sim/process.cc | |
parent | c11bcb8119273ef91c40a25b8fd9471a887d0ee5 (diff) | |
download | gem5-1f539f13c32ad5a9187d56a098d4c857639b0e05.tar.xz |
mem: Page Table map api modification
This patch adds uncacheable/cacheable and read-only/read-write attributes to
the map method of PageTableBase. It also modifies the constructor of TlbEntry
structs for all architectures to consider the new attributes.
Diffstat (limited to 'src/sim/process.cc')
-rw-r--r-- | src/sim/process.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/sim/process.cc b/src/sim/process.cc index f53c6b850..0412c27e0 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -338,7 +338,7 @@ Process::allocateMem(Addr vaddr, int64_t size, bool clobber) { int npages = divCeil(size, (int64_t)PageBytes); Addr paddr = system->allocPhysPages(npages); - pTable->map(vaddr, paddr, size, clobber); + pTable->map(vaddr, paddr, size, clobber ? PageTableBase::Clobber : 0); } bool @@ -553,9 +553,10 @@ Process::unserialize(Checkpoint *cp, const std::string §ion) bool -Process::map(Addr vaddr, Addr paddr, int size) +Process::map(Addr vaddr, Addr paddr, int size, bool cacheable) { - pTable->map(vaddr, paddr, size); + pTable->map(vaddr, paddr, size, + cacheable ? 0 : PageTableBase::Uncacheable); return true; } |