diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
commit | f85286b3debf4a4a94d3b959e5bb880be81bd692 (patch) | |
tree | 56a6be55a52d6cc6bb7e5d92fdcb25c79ad7d196 /src/sim/process.cc | |
parent | 06c39a154c4dc8fedcf9fbf77bbcf26f176c469c (diff) | |
download | gem5-f85286b3debf4a4a94d3b959e5bb880be81bd692.tar.xz |
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'src/sim/process.cc')
-rw-r--r-- | src/sim/process.cc | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/src/sim/process.cc b/src/sim/process.cc index 1714a87dc..239b4a3c5 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -45,7 +45,7 @@ #include "cpu/thread_context.hh" #include "mem/page_table.hh" #include "mem/physical.hh" -#include "mem/translating_port.hh" +#include "mem/se_translating_port_proxy.hh" #include "params/LiveProcess.hh" #include "params/Process.hh" #include "sim/debug.hh" @@ -244,12 +244,8 @@ Process::initState() // mark this context as active so it will start ticking. tc->activate(0); - Port *mem_port; - mem_port = system->physmem->getPort("functional"); - initVirtMem = new TranslatingPort("process init port", this, - TranslatingPort::Always); - mem_port->setPeer(initVirtMem); - initVirtMem->setPeer(mem_port); + initVirtMem = new SETranslatingPortProxy(*system->getSystemPort(), this, + SETranslatingPortProxy::Always); } // map simulator fd sim_fd to target fd tgt_fd |