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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-17 16:47:22 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-17 16:47:22 -0400 |
| commit | 4fff6d460311d77e0056a546df41366d5a3b4604 (patch) | |
| tree | e53419f2e4c6c38ff874e144d22fabeb9f637e6d /src/sim/process.hh | |
| parent | 6e8bfa4e63cd09b065b77166577104c06636b6f3 (diff) | |
| download | gem5-4fff6d460311d77e0056a546df41366d5a3b4604.tar.xz | |
Fixes to cache eliminating the assumption that the Packet is still valid after sending out a request.
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
Diffstat (limited to 'src/sim/process.hh')
0 files changed, 0 insertions, 0 deletions