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authorGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:01 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:01 -0800
commitc3d41a2def15cdaf2ac3984315f452dacc6a0884 (patch)
tree5324ebec3add54b934a841eee901983ac3463a7f /src/sim/process.hh
parentda2a4acc26ba264c3c4a12495776fd6a1c4fb133 (diff)
parent4acca8a0536d4445ed25b67edf571ae460446ab9 (diff)
downloadgem5-c3d41a2def15cdaf2ac3984315f452dacc6a0884.tar.xz
Merge with the main repo.
--HG-- rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'src/sim/process.hh')
-rw-r--r--src/sim/process.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/sim/process.hh b/src/sim/process.hh
index f738bb38a..3896492b7 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -48,7 +48,7 @@ class LiveProcessParams;
class SyscallDesc;
class System;
class ThreadContext;
-class TranslatingPort;
+class SETranslatingPortProxy;
template<class IntType>
struct AuxVector
@@ -123,7 +123,7 @@ class Process : public SimObject
protected:
/// Memory object for initialization (image loading)
- TranslatingPort *initVirtMem;
+ SETranslatingPortProxy *initVirtMem;
public:
PageTable *pTable;