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| author | Alexandru <alexandru.dutu@amd.com> | 2014-04-01 12:18:12 -0500 |
|---|---|---|
| committer | Alexandru <alexandru.dutu@amd.com> | 2014-04-01 12:18:12 -0500 |
| commit | 26ac28dec288e4fd96d999267ec7cafad4d58c5a (patch) | |
| tree | 937c3fc79a1d4622215c0e23ac6ae6e5945aab68 /src/sim/process.hh | |
| parent | 6dc90da08f5e743111ab9ae2623d5c0dad808d29 (diff) | |
| download | gem5-26ac28dec288e4fd96d999267ec7cafad4d58c5a.tar.xz | |
mem: adding a multi-level page table class
This patch defines a multi-level page table class that stores the page table in
system memory, consistent with ISA specifications. In this way, cpu models that
use the actual hardware to execute (e.g. KvmCPU), are able to traverse the page
table.
Diffstat (limited to 'src/sim/process.hh')
| -rw-r--r-- | src/sim/process.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/sim/process.hh b/src/sim/process.hh index be4c53dd9..361e07bca 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -1,4 +1,5 @@ /* + * Copyright (c) 2014 Advanced Micro Devices, Inc. * Copyright (c) 2001-2005 The Regents of The University of Michigan * All rights reserved. * @@ -124,7 +125,7 @@ class Process : public SimObject //separated. uint64_t M5_pid; - PageTable* pTable; + PageTableBase* pTable; class FdMap { |