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authorGabe Black <gblack@eecs.umich.edu>2006-10-12 10:58:45 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-12 10:58:45 -0400
commit866cfaf9dc596d8547e14bc2133fb962776572a7 (patch)
tree19b82a8021533e8bc2e35f14fb0b6a0440756814 /src/sim/pseudo_inst.cc
parent6a31898a88a9ecced399ccf50636831c21d4a75e (diff)
parent78aec04b660544ea7af80d76912b4422c4426602 (diff)
downloadgem5-866cfaf9dc596d8547e14bc2133fb962776572a7.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
Diffstat (limited to 'src/sim/pseudo_inst.cc')
-rw-r--r--src/sim/pseudo_inst.cc10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index b66c78b2c..addf897c6 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -138,14 +138,14 @@ namespace AlphaPseudo
void
m5exit_old(ThreadContext *tc)
{
- exitSimLoop(curTick, "m5_exit_old instruction encountered");
+ exitSimLoop("m5_exit_old instruction encountered");
}
void
m5exit(ThreadContext *tc, Tick delay)
{
Tick when = curTick + delay * Clock::Int::ns;
- exitSimLoop(when, "m5_exit instruction encountered");
+ schedExitSimLoop("m5_exit instruction encountered", when);
}
void
@@ -270,7 +270,11 @@ namespace AlphaPseudo
{
if (!doCheckpointInsts)
return;
- exitSimLoop("checkpoint");
+
+ Tick when = curTick + delay * Clock::Int::ns;
+ Tick repeat = period * Clock::Int::ns;
+
+ schedExitSimLoop("checkpoint", when, repeat);
}
uint64_t