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| author | Karthik Sangaiah <karthik.sangaiah@arm.com> | 2015-09-18 16:49:28 +0100 |
|---|---|---|
| committer | Karthik Sangaiah <karthik.sangaiah@arm.com> | 2015-09-18 16:49:28 +0100 |
| commit | 6fa936b021ac4d3030d20de5d037f1e7dd902cd9 (patch) | |
| tree | bbbaf5a03f3b79caeae43a6c7bc257dc208b3f52 /src/sim/pseudo_inst.cc | |
| parent | 413f3088eabf385507e854d74c0a5861e4d2856b (diff) | |
| download | gem5-6fa936b021ac4d3030d20de5d037f1e7dd902cd9.tar.xz | |
dev, arm: Add gem5 extensions to support more than 8 cores
Previous ARM-based simulations were limited to 8 cores due to
limitations in GICv2 and earlier. This changeset adds a set of
gem5-specific extensions that enable support for up to 256 cores.
When the gem5 extensions are enabled, the GIC uses CPU IDs instead of
a CPU bitmask in the GIC's register interface. To OS can enable the
extensions by setting bit 0x200 in ICDICTR.
This changeset is based on previous work by Matt Evans.
Diffstat (limited to 'src/sim/pseudo_inst.cc')
0 files changed, 0 insertions, 0 deletions