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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-25 18:23:17 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-08 15:28:12 +0000 |
| commit | 376f1b2ff7034f4d084a087a68307b11042d2a9d (patch) | |
| tree | 900b593a817104bc9345083f9952bbd3b8444bbf /src/sim/pseudo_inst.cc | |
| parent | 05ee4c5b53cd0eaee5725abf039285156dab2734 (diff) | |
| download | gem5-376f1b2ff7034f4d084a087a68307b11042d2a9d.tar.xz | |
arch-arm: Map ID_x_EL1 registers to AArch32 version
AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts. Those
registers must be initialized even when the highest Exception Level is
using AArch64.
Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10361
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/sim/pseudo_inst.cc')
0 files changed, 0 insertions, 0 deletions