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| author | Ali Saidi <saidi@eecs.umich.edu> | 2006-09-11 17:57:20 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-09-11 17:57:20 -0400 |
| commit | 46502851abffd70328ef605b1fa6056f873848e9 (patch) | |
| tree | c4572be025f11ac96b7ab6ed27317e8430498962 /src/sim/pseudo_inst.hh | |
| parent | 8bc3c2b19231df072fbc6d5dd29db612fff407dd (diff) | |
| download | gem5-46502851abffd70328ef605b1fa6056f873848e9.tar.xz | |
add annotation code to m5
configs/common/Benchmarks.py:
add annotate test app
src/SConscript:
add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
add annotate instructions
src/base/traceflags.py:
Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
add anotate ops
--HG--
extra : convert_revision : 7f965c0d84e41ce34f2ec8ec27a009276d67d8d6
Diffstat (limited to 'src/sim/pseudo_inst.hh')
| -rw-r--r-- | src/sim/pseudo_inst.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh index 4a83b93e0..da2fb4ee3 100644 --- a/src/sim/pseudo_inst.hh +++ b/src/sim/pseudo_inst.hh @@ -59,4 +59,6 @@ namespace AlphaPseudo void debugbreak(ThreadContext *tc); void switchcpu(ThreadContext *tc); void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr); + void anBegin(ThreadContext *tc, uint64_t cur); + void anWait(ThreadContext *tc, uint64_t cur, uint64_t wait); } |