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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
| commit | 50431f4eabc3894337586ca298a095643b3b6af0 (patch) | |
| tree | 35187ab64795905a82f181b663bf3487558a4d03 /src/sim/sim_events.hh | |
| parent | 16f210da3715bb69bed9a80a5cf0eeffec0edf7c (diff) | |
| download | gem5-50431f4eabc3894337586ca298a095643b3b6af0.tar.xz | |
ARM: Fix SRS instruction to micro-code memory operation and register update.
Previously the SRS instruction attempted to writeback in initiateAcc() which
worked until a recent change, but was incorrect.
Diffstat (limited to 'src/sim/sim_events.hh')
0 files changed, 0 insertions, 0 deletions