sim: Fix early termination in multi-core simulation under SE mode.

When "-I" (maximum instruction number) and "-F" (fastforward instruction
number) are applied together, gem5 immediately exits after the cpu switching.
The reason is that multiple exit events may be generated in the same cycle by
Atomic CPU and inserted to mainEventQueue. However, mainEventQueue can only
serve one exit event in one cycle. Therefore, the rest exit events are left in
mainEventQueue without being descheduled or deleted, which causes gem5 exits
immediately after the system resumes by cpu switching.

1 files changed, 14 insertions, 0 deletions

diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc
index 6962fab9f..fb785a91f 100644
--- a/src/sim/simulate.cc
+++ b/src/sim/simulate.cc
@@ -44,6 +44,10 @@
  * terminate the loop.  Exported to Python via SWIG.
  * @return The SimLoopExitEvent that caused the loop to exit.
  */
+
+// record the clock cycle for last exit event
+Tick lastExitTick = 0;
+
 SimLoopExitEvent *
 simulate(Tick num_cycles)
 {
@@ -67,6 +71,16 @@ simulate(Tick num_cycles)
 
         Event *exit_event = mainEventQueue.serviceOne();
         if (exit_event != NULL) {
+            /*
+             * if there are multiple exit events in the same cycle, drain the
+             * following exit events since gem5 only allows one * exit event in
+             * a cycle
+             */
+            if (lastExitTick == curTick())
+                continue;
+            else
+                lastExitTick = curTick();
+
             // hit some kind of exit event; return to Python
             // event must be subclass of SimLoopExitEvent...
             SimLoopExitEvent *se_event;