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authorAndreas Hansson <andreas.hansson@arm.com>2013-09-04 13:22:57 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-09-04 13:22:57 -0400
commit19a5b68db7d73542833d94ec8b23cad6daf0a787 (patch)
tree589541b322580a54e539e24932d3b4bba05801db /src/sim/system.cc
parentea402970185d5df01dbad2c0f41b8d76d2eb01cd (diff)
downloadgem5-19a5b68db7d73542833d94ec8b23cad6daf0a787.tar.xz
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. --HG-- rename : build_opts/NOISA => build_opts/NULL rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
Diffstat (limited to 'src/sim/system.cc')
-rw-r--r--src/sim/system.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 24f9dfbad..7de483216 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -48,7 +48,6 @@
#include "arch/isa_traits.hh"
#include "arch/remote_gdb.hh"
#include "arch/utility.hh"
-#include "arch/vtophys.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/str.hh"
@@ -228,6 +227,7 @@ System::registerThreadContext(ThreadContext *tc, int assigned)
threadContexts[id] = tc;
_numContexts++;
+#if THE_ISA != NULL_ISA
int port = getRemoteGDBPort();
if (port) {
RemoteGDB *rgdb = new RemoteGDB(this, tc);
@@ -243,6 +243,7 @@ System::registerThreadContext(ThreadContext *tc, int assigned)
remoteGDB[id] = rgdb;
}
+#endif
activeCpus.push_back(false);