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author | Lisa Hsu <hsul@eecs.umich.edu> | 2008-11-02 21:56:57 -0500 |
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committer | Lisa Hsu <hsul@eecs.umich.edu> | 2008-11-02 21:56:57 -0500 |
commit | c55a467a06eaa59c47c52a2adddc266b8e545589 (patch) | |
tree | e86f0c75e6009285507cd2414b829c122bb0be1f /src/sim/system.cc | |
parent | f4bceb9760c93d3b5ff3c2606f7e460b42724670 (diff) | |
download | gem5-c55a467a06eaa59c47c52a2adddc266b8e545589.tar.xz |
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
Diffstat (limited to 'src/sim/system.cc')
-rw-r--r-- | src/sim/system.cc | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/sim/system.cc b/src/sim/system.cc index 7b830d0f7..41075e9d0 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -166,13 +166,12 @@ bool System::breakpoint() } int -System::registerThreadContext(ThreadContext *tc, int id) +System::registerThreadContext(ThreadContext *tc) { - if (id == -1) { - for (id = 0; id < threadContexts.size(); id++) { - if (!threadContexts[id]) - break; - } + int id; + for (id = 0; id < threadContexts.size(); id++) { + if (!threadContexts[id]) + break; } if (threadContexts.size() <= id) |