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author | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:57 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:57 -0400 |
commit | 19a5b68db7d73542833d94ec8b23cad6daf0a787 (patch) | |
tree | 589541b322580a54e539e24932d3b4bba05801db /src/sim/system.hh | |
parent | ea402970185d5df01dbad2c0f41b8d76d2eb01cd (diff) | |
download | gem5-19a5b68db7d73542833d94ec8b23cad6daf0a787.tar.xz |
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.
The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.
--HG--
rename : build_opts/NOISA => build_opts/NULL
rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts
rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh
rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
Diffstat (limited to 'src/sim/system.hh')
-rw-r--r-- | src/sim/system.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/sim/system.hh b/src/sim/system.hh index 5058e7b26..5b166eabf 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -184,7 +184,9 @@ class System : public MemObject */ unsigned int cacheLineSize() const { return _cacheLineSize; } +#if THE_ISA != NULL_ISA PCEventQueue pcEventQueue; +#endif std::vector<ThreadContext *> threadContexts; int _numContexts; @@ -380,11 +382,13 @@ class System : public MemObject { Addr addr = 0; // initialize only to avoid compiler warning +#if THE_ISA != NULL_ISA if (symtab->findAddress(lbl, addr)) { T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), std::forward<Args>(args)...); return ev; } +#endif return NULL; } |