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author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
commit | d080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch) | |
tree | cc484b289fa5a30c4631f9faa1d8b456bffeebfc /src/sim/tlb.cc | |
parent | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff) | |
parent | 639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff) | |
download | gem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz |
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'src/sim/tlb.cc')
-rw-r--r-- | src/sim/tlb.cc | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/sim/tlb.cc b/src/sim/tlb.cc index 7292a69e0..e82e4f277 100644 --- a/src/sim/tlb.cc +++ b/src/sim/tlb.cc @@ -34,7 +34,7 @@ #include "sim/tlb.hh" Fault -GenericTLB::translate(RequestPtr req, ThreadContext * tc, bool) +GenericTLB::translateAtomic(RequestPtr req, ThreadContext * tc, bool) { #if FULL_SYSTEM panic("Generic translation shouldn't be used in full system mode.\n"); @@ -50,6 +50,14 @@ GenericTLB::translate(RequestPtr req, ThreadContext * tc, bool) } void +GenericTLB::translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, bool write) +{ + assert(translation); + translation->finish(translateAtomic(req, tc, write), req, tc, write); +} + +void GenericTLB::demapPage(Addr vaddr, uint64_t asn) { warn("Demapping pages in the generic TLB is unnecessary.\n"); |