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authorAli Saidi <Ali.Saidi@ARM.com>2012-09-25 11:49:40 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2012-09-25 11:49:40 -0500
commit0c99d21ad748371e801508a8c3652e07e2e56f93 (patch)
treea2a52170a8a88ce919cecb4309428999e5380cfd /src/sim/tlb.hh
parent29acf859ebde2cf219ae636f60d8a46db7a1bb94 (diff)
downloadgem5-0c99d21ad748371e801508a8c3652e07e2e56f93.tar.xz
ARM: Squash outstanding walks when instructions are squashed.
Diffstat (limited to 'src/sim/tlb.hh')
-rw-r--r--src/sim/tlb.hh7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index 379cdd343..0b89c9bd0 100644
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -94,6 +94,13 @@ class BaseTLB : public SimObject
*/
virtual void finish(Fault fault, RequestPtr req, ThreadContext *tc,
Mode mode) = 0;
+
+ /** This function is used by the page table walker to determine if it
+ * should translate the a pending request or if the underlying request
+ * has been squashed.
+ * @ return Is the instruction that requested this translation squashed?
+ */
+ virtual bool squashed() const { return false; }
};
};