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author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-06 10:19:36 -0700 |
commit | d080581db1f9ee4e1e6d07d2b01c13c67908a391 (patch) | |
tree | cc484b289fa5a30c4631f9faa1d8b456bffeebfc /src/sim/tlb.hh | |
parent | 7a7c4c5fca83a8d47c7e71c9c080a882ebe204a9 (diff) | |
parent | 639cb0a42d953ee32bc7e96b0cdfa96cd40e9fc1 (diff) | |
download | gem5-d080581db1f9ee4e1e6d07d2b01c13c67908a391.tar.xz |
Merge ARM into the head. ARM will compile but may not actually work.
Diffstat (limited to 'src/sim/tlb.hh')
-rw-r--r-- | src/sim/tlb.hh | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh index 011cc1144..8893f8c97 100644 --- a/src/sim/tlb.hh +++ b/src/sim/tlb.hh @@ -47,6 +47,21 @@ class BaseTLB : public SimObject public: virtual void demapPage(Addr vaddr, uint64_t asn) = 0; + + class Translation + { + public: + virtual ~Translation() + {} + + /* + * The memory for this object may be dynamically allocated, and it may + * be responsible for cleaning itself up which will happen in this + * function. Once it's called, the object is no longer valid. + */ + virtual void finish(Fault fault, RequestPtr req, + ThreadContext *tc, bool write=false) = 0; + }; }; class GenericTLB : public BaseTLB @@ -58,7 +73,9 @@ class GenericTLB : public BaseTLB public: void demapPage(Addr vaddr, uint64_t asn); - Fault translate(RequestPtr req, ThreadContext *tc, bool=false); + Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool=false); + void translateTiming(RequestPtr req, ThreadContext *tc, + Translation *translation, bool=false); }; #endif // __ARCH_SPARC_TLB_HH__ |