diff options
| author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:40 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:40 -0500 |
| commit | 94561dd5268d139b721561166cbce94170701c2c (patch) | |
| tree | 2e534ce3e0cdf0a9bbdec41978ef3bb775eb2929 /src/sim/tlb.hh | |
| parent | d44f2f611ff51941a8702a33a0bc57d7f574e462 (diff) | |
| download | gem5-94561dd5268d139b721561166cbce94170701c2c.tar.xz | |
arch: Add support for invalidating TLBs when draining
This patch adds support for the memInvalidate() drain method. TLB
flushing is requested by calling the virtual flushAll() method on the
TLB.
Note: This patch renames invalidateAll() to flushAll() on x86 and
SPARC to make the interface consistent across all supported
architectures.
Diffstat (limited to 'src/sim/tlb.hh')
| -rw-r--r-- | src/sim/tlb.hh | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh index aadf047bf..95a252e16 100644 --- a/src/sim/tlb.hh +++ b/src/sim/tlb.hh @@ -65,6 +65,11 @@ class BaseTLB : public SimObject virtual void demapPage(Addr vaddr, uint64_t asn) = 0; /** + * Remove all entries from the TLB + */ + virtual void flushAll() = 0; + + /** * Get the table walker master port if present. This is used for * migrating port connections during a CPU takeOverFrom() * call. For architectures that do not have a table walker, NULL @@ -75,6 +80,8 @@ class BaseTLB : public SimObject */ virtual BaseMasterPort* getMasterPort() { return NULL; } + void memInvalidate() { flushAll(); } + class Translation { public: |