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authorMin Kyu Jeong <minkyu.jeong@arm.com>2010-08-23 11:18:41 -0500
committerMin Kyu Jeong <minkyu.jeong@arm.com>2010-08-23 11:18:41 -0500
commit03286e9d4e797c7ca824a72627a947a42e01795f (patch)
tree6c873877ad9e5af85dcb7d319570c47d2622ad41 /src/sim
parent92ae620be8b46742042dcfe6dfaf38ecac24ad09 (diff)
downloadgem5-03286e9d4e797c7ca824a72627a947a42e01795f.tar.xz
CPU: Make Exec trace to print predication result (if false) for memory instructions
Diffstat (limited to 'src/sim')
-rw-r--r--src/sim/insttracer.hh4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index a8cdff671..c3f3eb323 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -58,6 +58,7 @@ class InstRecord
StaticInstPtr macroStaticInst;
MicroPC upc;
bool misspeculating;
+ bool predicate;
// The remaining fields are only valid for particular instruction
// types (e.g, addresses for memory ops) or when particular
@@ -102,6 +103,7 @@ class InstRecord
fetch_seq_valid = false;
cp_seq_valid = false;
+ predicate = false;
}
virtual ~InstRecord() { }
@@ -128,6 +130,8 @@ class InstRecord
void setCPSeq(InstSeqNum seq)
{ cp_seq = seq; cp_seq_valid = true; }
+ void setPredicate(bool val) { predicate = val; }
+
virtual void dump() = 0;
public: