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authorGiacomo Gabrielli <Giacomo.Gabrielli@arm.com>2011-02-11 18:29:35 -0600
committerGiacomo Gabrielli <Giacomo.Gabrielli@arm.com>2011-02-11 18:29:35 -0600
commite2507407b17188dca802082434cfe0230d9bfa61 (patch)
tree6913f9325a7c2fc9c6e99119c61f014e10707842 /src/sim
parent453dbc772dba92dbceb44eaeef3c617d17d63e84 (diff)
downloadgem5-e2507407b17188dca802082434cfe0230d9bfa61.tar.xz
O3: Enhance data address translation by supporting hardware page table walkers.
Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution.
Diffstat (limited to 'src/sim')
-rw-r--r--src/sim/tlb.hh18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index 1512bc0fa..253f12072 100644
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -64,6 +76,12 @@ class BaseTLB : public SimObject
virtual ~Translation()
{}
+ /**
+ * Signal that the translation has been delayed due to a hw page table
+ * walk.
+ */
+ virtual void markDelayed() = 0;
+
/*
* The memory for this object may be dynamically allocated, and it may
* be responsible for cleaning itself up which will happen in this