cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.

1 files changed, 8 insertions, 1 deletions

diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 6819c2199..3c954df26 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -58,6 +58,8 @@ namespace Trace {
 class InstRecord
 {
   protected:
+    typedef TheISA::VectorReg VectorReg;
+
     Tick when;
 
     // The following fields are initialized by the constructor and
@@ -97,6 +99,7 @@ class InstRecord
     union {
         uint64_t as_int;
         double as_double;
+        VectorReg as_vector;
     } data;
 
     /** @defgroup fetch_seq
@@ -120,7 +123,8 @@ class InstRecord
         DataInt16 = 2,
         DataInt32 = 4,
         DataInt64 = 8,
-        DataDouble = 3
+        DataDouble = 3,
+        DataVector = sizeof(VectorReg),
     } data_status;
 
     /** @ingroup memory
@@ -173,6 +177,8 @@ class InstRecord
     void setData(int8_t d)  { setData((uint8_t)d); }
 
     void setData(double d) { data.as_double = d; data_status = DataDouble; }
+    void setData(const VectorReg& v)
+    { data.as_vector = v; data_status = DataVector; }
 
     void setFetchSeq(InstSeqNum seq)
     { fetch_seq = seq; fetch_seq_valid = true; }
@@ -198,6 +204,7 @@ class InstRecord
 
     uint64_t getIntData() const { return data.as_int; }
     double getFloatData() const { return data.as_double; }
+    const VectorReg &getVectorData() const { return data.as_vector; }
     int getDataStatus() const { return data_status; }
 
     InstSeqNum getFetchSeq() const { return fetch_seq; }