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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-02-05 09:45:20 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-05-31 17:45:23 +0000 |
| commit | 51056cec69a72931a319e7be9370ea63f18e1aa3 (patch) | |
| tree | 9ba8760c4b488879674cfa715ac0b5fff1f4b36c /src/sim | |
| parent | 7d990bd25b478d906442ea63e1de6b381b51817b (diff) | |
| download | gem5-51056cec69a72931a319e7be9370ea63f18e1aa3.tar.xz | |
mem-cache: Add a non-coherent cache
The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.
This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>
Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Reviewed-on: https://gem5-review.googlesource.com/8291
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Diffstat (limited to 'src/sim')
0 files changed, 0 insertions, 0 deletions